PHY4635/5635 ADC Lab Page - Lab Portion of Final Exam, Spring 2008
Deadline: Saturday, May 3, 2008, 9:00am
Teams:
In the "real world", you will be required to work with others in developing designs. Please do
not dismiss the importance of team-based work - this is an essential skill set to have. Please
make sure that everyone on your team is thoroughly involved in all aspects of the work (including
yourself). Let Dr. Thaxton know about issues that may arise.
- Team A: Slagle, Abee, Robertson
- Team B: Moebus, Johnson, Madison
- Team C: Mount, McBrayer, Maples
Objective:
Design, build, test, and demonstrate an operational voltmeter.
Design description:
The design should implement an analog-to-digital converter (8-bit resolution, minimum) that samples
a continuous voltage source in the range 0.0VDC - 5.0VDC. The interface is the PC parallel port
(0378h-037Bh).
Deliverables:
A working design that can be demonstrated. A 1-2 page report on the design.
Include the roles that everyone on the team had - for example, "Phyllis was responsible for the GUI design and
coding, Elliot was primarily responsible for the ADC (altough we all helped), and Ji-Fu was responsible
for the parallel port protocol design and report writing (we all contributed our portions)." The report
should include as appendices a schematic of your design, a bill of materials (need not include prices), and the assembly source code (commented).
Grading:
Everyone on a given team will be given the same grade for the team's work. If the system
is operational and conforms to the stated specifications (see below), the team will receive a 100%. If the
design is well-thought out and presented well but doesn't work, the team will receive an 85-95% (depending on
how close it was to working). If the team produces a poor design that doesn't work and is poorly presented,
the team will receive a 65%. Anything better than this will warrant a grade in the range 65%-85%, depending
on the quality of design and how close it is to working.
Recognition:
The winning team will be published in the forth-coming Lab Manual for PHY 4635 / 5635 and
can use this citation in their respective CVs.
Design specifications:
The design should employ an 8-bit (minimum) AD-conveter that takes as input a continuous,
TTL-level voltage 0-5VDC. You can generate this input voltage from a DC supply and/or a potentiometer if you'd like.
The ADC that you will use is the ADC0804 or the ADC0820. If using the ADC0820, you need not employ the hold function.
You will need to input the 8 data bits from the parallel port (but recall that 0378h is an OUTPUT port). You *may* also have to output
control signals to latches, etc., so please review the bit and pin definitions on the following handout:
bumgarner.pdf
This is a working example of implementing the ADC0809 - review it CAREFULLY.
The GUI should be rather simple - when the program is initiated, you just need to display to the screen a message saying
what the program is doing and the voltage reading that corresponds to the current
voltage being detected. The challenge here is (i) to calibrate your system to 0 volts and (ii) convert your hex
representation of the voltgage into ASCII values. The resolution of the output should be 0.1VDC. The voltage reading
should be continuously updated (overwitten) on the screen, in the form 3.2VDC, for example. See Dr. Thaxton if
you are having trouble with this aspect of the design.
Resources:
You may use the bread-boards, wiring, and any other ICs or circuit elements that you can find in the lab and deem necessary, on a first come,
first served, finders-keepers basis.
IMPORTANT: See Dr. Thaxton to get the any of the ICs listed below once you have chosen which
one's you want to use - due to the limited numbers of ICs, you will not receive an IC unless you can demonstrate
that is it part of your design.
Datasheets for various ICs that are available to you.
- 74LS240: Octal Buffer/Line Driver with 3-State Outputs
- 74LS241: Octal 3-STATE Buffer/Line Driver/Line Receiver
- 74LS244: Octal TRI-STATE Buffers/Line Drivers/Line Receivers
- 74LS245: OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
- 74LS00: QUADRUPLE 2-INPUT POSITIVE-NAND GATES
- 74LS04: Hex Inverters
- 74HCT14: Hex inverting Schmitt trigger
- AD7512: CMOS protected analog switches
- ADC0804: 8-Bit, Microprocessor-Compatible, A/D Converters
- ADC0820: 8-Bit High Speed uP Compatible A/D Converter with Track/Hold Function